The DV Challenge was well set up and a very low barrier to entry. My research background lies in ML for physical design, so my experience with the cache controller was very limited. The help page was useful in providing enough information for me to understand the basics and proceed. The challenge got extremely competitive towards the end which brought the best out of me to try and optimize the hyperparameters. The contest was both fun and insightful.
This DV challenge was such a niche one targeting a specific set of people. Possessing very little ML knowledge, it was a great learning experience for me as I understood the nuances of hyperparameter tuning and their importance in a field like DV. Seeing the massive response and competition towards the end of the challenge I even learned the art of not giving up. Looking forward to more such challenges in the future.
My experience with VerifAI DV Challenge was phenomenal. It helped me realize how important Machine learning is, for the Design Verification. I liked the webapp interface very much, it has helped me save a lot of time and concentrate more on the logic. Overall, it was a great experience and i am glad that i have secured 3rd place in such a highly competitive DV Challenge.
The VerifAI DV Challenge was a great opportunity to become more familiar with the underlying technology in VerifAI's products. As an ASIC Designer, it is not often that you have an opportunity to better understand the tools that you use. This challenge gave me the opportunity to twist some of the knobs and understand how these adjustments affected the outcome of the algorithms. With this new knowledge, I will be better suited to use VerifAI's products, which will in turn improve WD's products and our ASIC development workflow.
The tremendous advances in Integrated Circuit (IC) Design has brought us great products over the last decade. These advances in IC's have also increased the complexity of Design Verification significantly. Design Verification (DV), the process of verifying that an IC functions as intended, takes up more than 50% of the time and cost of designing an IC (Reference: Research study by Siemens). Costs of DV are increasing, and, the time-to-market for new IC projects are slipping due to DV. To meet the growing demand for IC's we need to find innovative ways to speed up verification and reduce the associated costs. Additionally, as the research highlights, DV requires a significant amount of engineering talent and, the demand for DV Engineers grew at a 6.8% CAGR. There are not enough DV engineers being produced to meet this demand. Using innovative Machine Learning approaches presents significant opportunities to accelerate innovation in DV.
The Objective of this DV Challenge is for participants to use innovative Machine Learning techniques to speed up verification and find bugs faster. The goal in this challenge is to maximize the average FIFO depths in a MESI Cache Controller Design. There are 4 FIFO Queues in this Cache Controller, one for each CPU. Each FIFO queue can hold up to 16 entries. The goal is to maximize the number of entries in each FIFO. Simply put, the higher average FIFO depth across all 4 queues the better are our chances of finding hard bugs. Participants can tune the Machine Learning Hyper-parameters and DV Knobs (settings) to increase the FIFO depths. VerifAI's Machine Learning Platform helps DV Engineers speed up verification. Finding bugs faster and Speeding up DV, reduces costs and improves time to market significantly.
Apple Watch Series 6
Participant registration opens
DV Challenge #1 closes
Prize is announced